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| M58MR032C M58MR032D 32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory PRELIMINARY DATA s SUPPLY VOLTAGE - VDD = VDDQ = 1.7V to 2.0V for Program, Erase and Read s s - VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ - Burst mode Read: 40MHz - Page mode Read (4 Words Page) - Random Access: 100ns FBGA TFBGA48 (ZC) 10 x 4 ball array s PROGRAMMING TIME - 10s by Word typical - Two or four words programming option s MEMORY BLOCKS - Dual Bank Memory Array: 8/24 Mbit - Parameter Blocks (Top or Bottom location) Figure 1. Logic Diagram s DUAL OPERATIONS - Read within one Bank while Program or Erase within the other - No delay between Read and Write operations VDD VDDQ VPP 5 A16-A20 W E G RP WP L K M58MR032C M58MR032D BINV WAIT 16 ADQ0-ADQ15 s PROTECTION/SECURITY - All Blocks protected at Power-up - Any combination of Blocks can be protected - 64 bit unique device identifier - 64 bit user programmable OTP cells - One parameter block permanently lockable s s COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M58MR032C: 88DAh - Bottom Device Code, M58MR032D: 88DBh s VSS AI90019 August 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/52 M58MR032C, M58MR032D Figure 2. TFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DU DU B DU DU C WAIT NC VSS K VDD W VPP A19 A17 NC D VDDQ A16 A20 L BINV RP WP A18 E VSS E VSS ADQ7 ADQ6 ADQ13 ADQ12 ADQ3 ADQ2 ADQ9 ADQ8 G F ADQ15 ADQ14 VSS ADQ5 ADQ4 ADQ11 ADQ10 VDDQ ADQ1 ADQ0 G DU DU H DU DU AI90020 DESCRIPTION The M58MR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-byWord basis using a 1.7V to 2.0V V DD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports synchronous burst read and asynchronous read from all the blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at each clock cycle for frequencies up to 40MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up. Blocks can be unprotected to make changes in the application and then re-protected. A parameter block "Security block" can be permanently protected against programming and erasing in order to increase the data security. An optional 12V V PP power supply is provided to speed up the program phase at costumer production. An internal command interface (C.I.) decodes the instructions to access/modify the memory content. The program/erase controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Two status registers indicate the state of each bank. Instructions for Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Write Read Configuration Register, Program, Block Erase, Bank Erase, Program Suspend, Program Resume, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, Protection Program, CFI Query, are written to the memory through a Command Interface (C.I.) using standard micro-processor write timings. The memory is offered in TFBGA48, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to '1'). 2/52 M58MR032C, M58MR032D Table 1. Signal Names A16-A20 ADQ0-ADQ15 E G W RP WP K L WAIT BINV VDD VDDQ VPP VSS DU NC Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power-down Write Protect Burst Clock Latch Enable Wait Data in Burst Mode Bus Invert Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Don't Use as Internally Connected Not Connected Internally Organization The M58MR032 is organized as 2Mb by 16 bits. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A20 are the MSB addresses. Chip Enable E, Output Enable G and Write Enable W inputs provide memory control. The clock K input synchronizes the memory to the microprocessor during burst read. Reset RP is used to reset all the memory circuitry and to set the chip in power-down mode if a proper setting of the Read Configuration Register enables this function. WAIT output indicates to the microprocessor the status of the memory during the burst mode operations. Memory Blocks The device features asymmetrically blocked architecture. M58MR032 has an array of 71 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. Only one bank at the time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The memory features an erase suspend allowing reading or programming in another block. Once suspended the erase can be resumed. Program can be suspended to read data in another block and then resumed. The Bank Size and sectorization are summarized in Table 3. Parameter Blocks are located at the top of the memory address space for the M58MR032C, and at the bottom for the M58MR032D. The memory maps are shown in Figure 3. Value -40 to 85 -40 to 125 -55 to 155 -0.5 to VDDQ+0.5 -0.5 to 2.7 -0.5 to 13 Unit C C C V V V Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (3) VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. 3. Minimum Voltage may undershoot to -2V during transition and for less than 20ns. 3/52 M58MR032C, M58MR032D The architecture includes a 128 bits Protection register that is divided into two 64-bits segments. In the first one is written a unique device number, while the second one is programmable by the user. The user programmable segment can be permanently protected programming the bit 1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected Table 3. Bank Size and Sectorization Bank Size Bank A Bank B 8 Mbit 24 Mbit Parameter Blocks 8 blocks of 4 KWord Main Blocks 15 blocks of 32 KWord 48 blocks of 32 KWord by the user programming the bit 2 of the Protection Lock Register. Block protection against Program or Erase provides additional data security. All blocks are protected and unlocked at Power-up. Instructions are provided to protect or un-protect any block in the application. A second register locks the protection status while WP is low (see Block Locking description). Figure 3. Memory Map Top Boot Block Address lines A20-A0 000000h 007FFFh Bank B 512 Kbit or 32 KWord Total of 48 Main Blocks 000000h 000FFFh Bottom Boot Block Address lines A20-A0 64 Kbit or 4 KWord Total of 8 Parameter Blocks 007000h Bank A 512 Kbit or 32 KWord Total of 15 Main Blocks 007FFFh 008000h 00FFFFh 64 Kbit or 4 KWord 512 Kbit or 32 KWord Total of 15 Main Blocks 178000h 17FFFFh 180000h 187FFFh 512 Kbit or 32 KWord 1F0000h Bank A 1F7FFFh 1F8000h 1F8FFFh 512 Kbit or 32 KWord 64 Kbit or 4 KWord Total of 8 Parameter Blocks 078000h 07FFFFh 080000h 087FFFh Bank B 512 Kbit or 32 KWord 512 Kbit or 32 KWord Total of 48 Main Blocks 1FF000h 1FFFFFh 64 Kbit or 4 KWord 1F8000h 1FFFFFh 512 Kbit or 32 KWord AI90069 4/52 M58MR032C, M58MR032D SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0ADQ15). When Chip Enable E is at VIL and Output Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memory array, data to be programmed in the memory array or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. In synchronous operations the address is also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. Both input data and commands are latched on the rising edge of Write Enable W. When Chip Enable E and Output Enable G are at V IL the address/data bus outputs data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection status the Read Configuration Register status, the protection register or the Status Register. The address/data bus is high impedance when the chip is deselected, Output Enable G is at V IH, or RP is at VIL. Address Inputs (A16-A20). The five MSB addresses of the memory array are latched on the rising edge of Latch Enable L. In synchronous operation these inputs are also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at V IL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is at VIH the outputs are High impedance. Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power-down Input (RP). The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Read Configuration Register status. Reset/Power-down of the memory is achieved by pulling RP to V IL for at least tPLPH. When the reset pulse is given, the memory will recover from Power-down (when enabled) in a minimum of t PHEL, tPHLL or tPHWL (see Table 31 and Figure 15) after the rising edge of RP. Exit from Reset/Power-down changes the contents of the Read Configuration Register bits 14 and 15, setting the memory in asynchronous page mode read and power save function disabled. All blocks are protected and unlocked after a Reset/Power-down. Latch Enable (L). L latches the address bits ADQ0-ADQ15 and A16-A20 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at V IH. Clock (K). The clock input synchronizes the memory to the micro controller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration settings) when L is at VIL. K is don't care during asynchronous page mode read and in write operations. Wait (WAIT). WAIT is an output signal used during burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cycle in advance. Bus Invert (BINV). BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previous data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at VOH to inform the receiving system that data must be inverted before any further processing. By doing so, the actual transitions on the data bus will be less than 8. In a similar way, when a command is given, BINV may be driven by the system at VIH to inform the memory that the data input must be inverted. Like the other input/output pins, BINV is high impedance when the chip is deselected, output enable G is at VIH or RP is at VIL; when used as an input, BINV must follow the same set-up and hold timings of the data inputs. VDD and V DDQ Supply Voltage (1.7V to 2.0V). VDD is the main power supply for all operations (Read, Program and Erase). VDDQ is the supply voltage for Input and Output. 5/52 M58MR032C, M58MR032D VPP Program Supply Voltage (12V). VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin; if VPP is kept in a low voltage range (0 to 2V) V PP is seen as a control input, and the current absorption is limited to 5A (0.2A typical). In this case with VPP = VIL we obtain an absolute protection against program or erase; with V PP = VPP1 these functions are enabled (see Table 26). VPP value is only sampled during program or erase write cycles; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. If V PP is used in the 11.4V to 12.6V range (VPPH) then the pin acts as a power supply (see Table 26). This supply voltage must remain stable as long as program or erase are running. In read mode the current sunk is less then 0.5mA, while during program and erase operations the current may increase up to 10mA. VSS Ground. VSS is the reference for all the voltage measurements. 6/52 M58MR032C, M58MR032D DEVICE OPERATIONS The following operations can be performed using the appropriate bus cycles: Address Latch, Read Array (Random, and Page Modes), Write command, Output Disable, Standby, reset/Powerdown and Block Locking. See Table 4. Address Latch. In asynchronous operation, the address is latched on the rising edge of L input. In burst mode the address is latched either on the rising edge of L or on the first rising/falling edge of K (depending on configuration settings) when L is low. Read. Read operations are used to output the contents of the Memory Array, the Electronic SigTable 4. User Bus Operations (1) Operation Address Latch Write Output Disable Standby Reset / Power-down Block Locking Note: 1. X = Don't care. nature, the Status Register, the CFI, the Block Protection Status, the Read Configuration Register status and the Protection Register. Read operation of the Memory Array may be performed in asynchronous page mode or synchronous burst mode. In asynchronous page mode data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by ADQ0 and ADQ1 address inputs. According to the device configuration the following Read operations: Electronic Signature - Status Register - CFI - Block Protection Status - Read Configuration Register Status - Protection Register must be accessed as asynchronous read or as single synchronous read (see Figure 4). L VIL (rising edge) VIH VIH X X X RP VIH VIH VIH VIH VIL VIH WP VIH VIH VIH X X VIL ADQ15-ADQ0 Address Input Data Input Hi-Z Hi-Z Hi-Z X E VIL VIL VIL VIH X VIL G VIH VIH VIH X X X W VIH VIL VIH X X X Table 5. Read Electronic Signature (AS and Read CFI instructions) (1) Code Manufacturer Code M58MR032C Device Code M58MR032D VIL VIL VIH VIL VIH EA (2) 88DBh Note: 1. Addresses are latched on the rising edge of L input. 2. EA means Electronic Signature Address (see Read Electronic Signature) 3. Value during address latch. Device E VIL VIL G VIL VIL W VIH VIH ADQ1 (3) VIL VIL ADQ0 (3) VIL VIH Other Address (2) EA (2) EA (2) ADQ15-0 0020h 88DAh Table 6. Read Block Protection (AS and Read CFI instructions) (1) Block Status Protected and unlocked Unprotected and unlocked Protected and locked Unprotected and locked (2) Note: 1. 2. 3. 4. E VIL VIL VIL VIL G VIL VIL VIL VIL W VIH VIH VIH VIH ADQ1 (3) VIH VIH VIH VIH ADQ0 (3) VIL VIL VIL VIL Other Address BA (4) BA (4) BA (4) BA (4) ADQ15-0 0001 0000 0003 0002 Addresses are latched on the rising edge of L input. A locked block can be unprotected only with WP at VIH. Value during address latch. BA means Block Address. First cycle command address should indicate the bank of the block address. 7/52 M58MR032C, M58MR032D Table 7. Read Protection Register (RSIG and RCFI Instruction) (1) Word Lock Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 E VIL VIL VIL VIL VIL VIL VIL VIL VIL G VIL VIL VIL VIL VIL VIL VIL VIL VIL W VIH VIH VIH VIH VIH VIH VIH VIH VIH A20-17 X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) ADQ15-8 X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) ADQ7-0 80h 81h 82h 83h 84h 85h 86h 87h 88h ADQ15-8 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data ADQ7-3 00000B ID data ID data ID data ID data OTP data OTP data OTP data OTP data ADQ2 Security prot.data ID data ID data ID data ID data OTP data OTP data OTP data OTP data ADQ1 OTP prot.data ID data ID data ID data ID data OTP data OTP data OTP data OTP data ADQ0 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data Note: 1. Addresses are latched on the rising edge of L input. 2. X = Don't care. Table 8. Dual Bank Operations (1, 2, 3) Commands allowed in the other bank Status of one bank Read Array Yes - Yes Yes Yes Yes Read Status Yes - Yes Yes Yes Yes Read ID/CFI Yes - Yes Yes Yes Yes Program Yes - - - - Yes Erase/ Erase Resume Yes - - - - - Program Suspend Yes - - - - Yes Erase Suspend Yes - - - - - Protect Unprotect Yes - Yes Yes Yes Yes Idle Reading Programming Erasing Program Suspended Erase Suspended Note: 1. For detailed description of command see Table 33 and 34. 2. There is a status register for each bank; status register indicates bank state, not P/E.C. status. 3. Command must be written to an address within the block targeted by that command. 8/52 M58MR032C, M58MR032D Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions) K L A20-A16 VALID ADDRESS CONF. CODE 2 ADQ15-ADQ0 VALID ADDRESS VALID DATA NOT VALID NOT VALID NOT VALID CONFIGURATION CODE 3 ADQ15-ADQ0 VALID ADDRESS CONFIGURATION CODE 4 ADQ15-ADQ0 VALID ADDRESS VALID DATA NOT VALID VALID DATA NOT VALID NOT VALID AI90022 Both Chip Enable E and Output Enable G must be at VIL in order to read the output of the memory. Read array is the default state of the device when exiting power down or after power up. Burst Read. The device also supports a burst read. In this mode a burst sequence is started at the first clock edge (rising or falling according to configuration settings) after the falling edge of L. After a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. The burst sequence may be configured for linear or interleaved order and for a length of 4, 8 words or for continuous burst mode. Wrap and no-wrap modes are also supported. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. See the Write Read Configuration Register (CR) Instruction for more details on all the possible settings for the synchronous burst read (see Table 14). It is possible to perform burst read across bank boundary (all banks in read array mode). Write. Write operations are used to give Instruction Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at V IL with Output Enable G at VIH. Addresses are latched on the rising edge of L. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Noise pulses of less than 5ns typical on E, W and G signals do not start a write cycle. Write operations are asynchronous and clock is ignored during write. Dual Bank Operations. The Dual Bank allows to run different operations simultaneously in the two banks. It is possible to read array data from one bank while the other is programming, erasing or reading any data (CFI, status register or electronic signature). Read and write cycles can be initiated for simultaneous operations in different banks without any delay. Only one bank at a time is allowed to be in program or erase mode, while the other must be in one of the read modes (see Table 8). Commands must be written to an address within the block targeted by that command. Output Disable. The data outputs are high impedance when the Output Enable G is at V IH with Write Enable W at VIH. Standby. The memory is in standby when Chip Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. The automatic standby feature is not available when the device is configured for synchronous burst mode. 9/52 M58MR032C, M58MR032D Table 9. Identifier Codes Code Manufacturer Code Top Device Code Bottom Protected and Unlocked Unprotected and Unlocked Block Protection Protected and Locked Unprotected and Locked Die Revision Code Read Configuration Register Lock Protection Register Protection Register Bank Address + 03 Bank Address + 05 Bank Address + 80 Bank Address + 81 Bank Address + 88 Bank Address + 02 0003 0002 DRC (1) CR (1) LPR (1) PR (1) Bank Address + 01 88DB 0001 0000 Address (h) Bank Address + 00 Bank Address + 01 Data (h) 0020 88DA Note: 1. DRC means Die Revision Code. CR means Read Configuration Register. LPR means Lock Protection Register. PR means Unique Device Number and User Programmable OTP. Reset/Power-down. The memory is in Powerdown when the Read Configuration Register is set for Power-down and RP is at V IL. The power consumption is reduced to the Power-down level, and Outputs are in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs. The memory is in reset when the Read Configuration Register is set for Reset and RP is at VIL. The power consumption is the same of the standby and the outputs are in high impedance. After a Reset/Power down the device defaults to read array mode, the status register is set to 80h and the read configuration register defaults to asynchronous read. Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to V IL. The following summarizes the locking operation. All blocks are protected on power-up. They can then be unprotected or protected with the Unprotect and Protect commands. The Lock command protects a block and prevents it from being unlocked when WP = 0. When WP = 1, Lock is overridden. Lock is cleared only when the device is reset or powered-down (see Protect instruction). 10/52 M58MR032C, M58MR032D INSTRUCTIONS AND COMMANDS Eighteen instructions are available (see Tables 10 and 11) to perform Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Block Erase, Bank Erase, Program, Tetra Word Program, Double Word Program, Clear Status Register, Program/Erase Suspend, Program/ Erase Resume, Block Protect, Block Unprotect, Block Lock, Protection Register Program, Read Configuration Register and Lock Protection Program. Status Register output may be read at any time, during programming or erase, to monitor the progress of the operation. An internal Command Interface (C.I.) decodes the instructions while an internal Program/Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Register whose bits indicate operation and exit status of the internal algorithms. The Command Interface is reset to Read Array when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO . Command sequence must be followed exactly. Any invalid combination of commands will reset the device to Read Array. Read (RD) The Read instruction consists of one write cycle (refer to Device Operations section) and places the addressed bank in Read Array mode. When a device reset occurs, the memory is in Read Array as default. A read array command will be ignored while a bank is programming or erasing. However in the other bank a read array command will be accepted. Read Status Register (RSR) A bank's Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register Instruction (70h) to read the Status Register content of the addressed bank. The status of the other bank is not affected by the command. The Read Status Register instruction may be issued at any time, also when a Program/Erase operation is ongoing. The following Read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. Read Electronic Signature (RSIG) The Read Electronic Signature instruction consists of one write cycle (refer to Device Operations section) giving the command 90h to an address Table 10. Commands Hex Code 00h 01h 03h 10h 20h 2Fh 30h 40h 50h 55h 60h 70h 80h 90h 98h B0h C0h D0h FFh Invalid Reset Protect Confirm Write Read Configuration Register Confirm Alternative Program Set-up Block Erase Set-up Lock Confirm Double Word Program Set-up Program Set-up Clear Status Register Tetra Word Program Set-up Protect Set-up and Write Read Configuration Register Read Status Register Bank Erase Set-up Read Electronic Signature CFI Query Program/Erase Suspend Protection Program and Lock Protection Program Program/Erase Resume, Erase Confirm or Unprotect Confirm Read Array Command within the bank A. A subsequent read in the address of bank A will output the Manufacturer Code, the Device Code, the protection Status of Blocks of bank A, the Die Revision Code, the Protection Register, or the Read Configuration Register (see Table 9). If the first write cycle of Read Electronic Signature instruction is issued to an address within the bank B, a subsequent read in an address of bank B will output the protection Status of Blocks of bank B. The status of the other bank is not affected by the command (see Table 8). See Tables 5, 6, 7 and 8 for the valid address. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M58MR032C and M58MR032D. 11/52 M58MR032C, M58MR032D Table 11. Instructions Instruction Read Memory Array Read Status Register Read Electronic Signature Read CFI Cyc. Operation Address (1,2) Data (3) Operation Address (1,2) Data (3) RD 1+ Write BKA FFh Read (1) Read (1) Read (1) Read (1) Read Address BKA Data Status Register ED CD RSR READ 1+ Write BKA 70h RSIG RCFI 1+ 1+ 1 2 2 2 3 Write Write Write Write Write Write Write EA CA BKA BA BKA WA WA1 90h 98h 50h 20h 80h 40h or 10h 30h EA CA Clear Status CLRS (5) Register EE BE PG DPG PROGRAM/ERASE Block Erase Bank Erase Program Double Word Program Write Write Write Write Write BA BKA WA WA1 WA2 WA1 WA2 WA3 WA4 D0h D0h WD WD1 WD2 WD1 WD2 WD3 WD4 TPG Tetra Word Program 5 Write WA1 55h Write Write Write Write PES Program Erase Suspend Program Erase Resume Block Protect Block Unprotect Block Lock Protection Register Program Lock Protection Register Program Write Read Configuration Register 1 Write BKA B0h PER BP BU BL PRP CONFIGURATION 1 2 2 2 2 Write Write Write Write Write BKA BA BA BA PA D0h 60h 60h 60h C0h Write Write Write Write BA BA BA PA 01h D0h 2Fh PD PROTECT LPRP 2 Write LPA C0h Write LPA LPD CR 2 Write RCA 60h Write RCA 03h 12/52 M58MR032C, M58MR032D Note: 1. First cycle command address should be the same as the operation's target address. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one command cycle. 2. BKA means Address within the bank; BA means Block Address; EA means Electronic Signature Address; CA means Common Flash Interface Address; WA means Word Address; PA means Protection Register Address (see Table 7); LPA means Lock Protection Register Address (see Table 7); RCA means Read Configuration Register Address. 3. PD means Protection Data; CD means Common Flash Interface Data; ED means Electronic Signature Data; WD means Data to be programmed at the address location WA; LPD means Lock protection Register Data 4. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0. 5. Read cycle after e CLSR instruction will output the memory array. CFI Query (RCFI) The CFI Query Mode is associated to bank A. The address of the first write cycle must be within the bank A. The status of the other bank is not affected by the command (see Table 8). Writing 98h the device enters the Common Flash Interface Query mode. Next read operations in the bank A will read the CFI data. Write a read instruction to return to Read mode (refer to the Common Flash Interface section). Clear Status Register (CLSR) The Clear Status Register uses a single write operation, which resets bits b1, b3, b4 e b5 of the status register. The Clear Status Register is executed writing the command 50h independently of the applied VPP voltage. After executing this command the device returns to read array mode. The Clear Status Register command clears only the status register of the addressed bank. Block Erase (EE) Block erasure sets all the bits within the selected block to '1'. One block at a time can be erased. It is not necessary to pre-program the block as the P/E.C. will do it automatically before erasing. This instruction use two writes cycles. The first command written is the Block Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased should be given to the memory during the two cycles command. If the second command given is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. After writing the command, the device outputs status register data when any address within the bank is read. At the end of the operation the bank will remain in read status register until a read array command is written. Status Register bit b7 is '0' while the erasure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if there has been an Erase Failure. Status register bit b1 returns '1' if the user is attempting to erase a protected block. Status Register bit b3 returns a '1' if VPP is below V PPLK. Erase aborts if RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated (see Table 12). A Clear Status Register instruction must be issued to reset b1, b3, b4 and b5 of the Status Register. During the execution of the erase by the P/E.C., the bank with the block in erase accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. See figure 19 for Erase Flowchart and Pseudo Code. Bank Erase (BE) Bank erase sets all the bits within the selected bank to '1'. It is not necessary to pre-program the block as the P/E.C. will do it automatically before erasing. This instruction uses two writes cycles. The first command written is the Bank Erase set-up command 80h. The second command is the Erase Confirm command D0h. An address within the bank to be erased should be given to the memory during the two cycles command. See the Block Erase command section for status register bit details. 13/52 M58MR032C, M58MR032D Table 12. Status Register Bits Mnemonic P/ECS Bit 7 Name P/ECS Status Logic Level 1 0 ESS 6 Erase Suspend Status Erase Status Program Status 1 0 1 0 PS 4 1 0 VPPS 3 VPP Status 1 0 PSS 2 Program Suspend Status Block Protection Status 1 0 Definition Ready Busy Suspended In Progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Suspended In Progress or Completed Program/Erase on protected Block, Abort PS bit set to '1' if the P/E.C. has failed to program a word. VPPS bit is set if the VPP voltage is below VPPLK when a Program or Erase instruction is executed. VPP is sampled only at the beginning of the erase/program operation. On a program Suspend instruction P/ECS and PSS bits are set to '1'. PSS remains '1' until a Program Resume Instruction is given. Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success. On an Erase Suspend instruction P/ECS and ESS bits are set to '1'. ESS bit remains '1' until an Erase Resume instruction is given. ES bit is set to '1' if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. ES 5 BPS 1 1 0 0 Reserved BPS bit is set to '1' if a Program or Erase operation has been attempted on a protected No operation to block. protected blocks Note: Logic level '1' is VIH and '0' is VIL. Program (PG) The Program instruction programs the array on a word-by-word basis. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure (see Table 12). Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if V PP is below VPPLK. Any attempt to write a '1' to an already programmed bit will result in a program fail (status register bit b4 set) if V PP = V PPH and will be ignored if V PP = VPP1. Programming aborts if RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. See Figure 16 for Program Flowchart and Pseudo Code. 14/52 M58MR032C, M58MR032D Figure 5. Security Block Memory Map 88h User Programmable OTP 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number AI90023 Table 13. Protection States (1) Current State (2) (WP, DQ1, DQ0) 100 101 110 111 000 001 011 Program/Erase Allowed Yes No Yes No Yes No No Next State After Event (3) Protect 101 101 111 111 001 001 011 Unprotect 100 100 110 110 000 000 011 Lock 111 111 111 111 011 011 011 WP transition 000 001 011 011 100 101 111 or 110 (4) Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect in and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = VIH and A0 = V IL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value. 4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. 15/52 M58MR032C, M58MR032D Double Word Program (DPG) This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). The two words must differ only for the address A0. Programming should not be attempted when VPP is not at V PPH. The operation can also be executed if V PP is below V PPH but result could be uncertain. These instruction uses three write cycles. The first command written is the Double Word Program Set-Up command 30h. A second write operation latches the Address and the Data of the first word to be written, the third write operation latches the Address and the Data of the second word to be written and starts the P/E.C. (see Table 11). Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Any attempt to write a '1' to an already programmed bit will result in a program fail (status register bit b4 set). (See Table 12). Programming aborts if RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Double Word Program Flowchart and Pseudo code. Tetra Word Program (TPG) This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH but result could be uncertain. These instruction uses five write cycles. The first command written is the Tetra Word Program Set-Up command 55h. A second write operation latches the Address and the Data of the first word to be written, the third write operation 16/52 latches the Address and the Data of the second word to be written, the fourth write operation latches the Address and the Data of the third word to be written, the fifth write operation latches the Address and the Data of the fourth word to be written and starts the P/E.C. (see Table 11). Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Any attempt to write a '1' to an already programmed bit will result in a program fail (status register bit b4 set). (See Table 12). Programming aborts if RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Tetra Word Program Flowchart and Pseudo code. Erase Suspend/Resume (PES/PER) The Erase Suspend freezes, after a certain latency period (within 25us), the erase operation and allows read in another block within the targeted bank or program in the other block. This instruction uses one write cycle B0h and the address should be within the bank with the block in erase (see Table 11). The device continues to output status register data after the erase suspend is issued. The status register bit b7 and bit b6 are set to '1' then the erase operation has been suspended. Bit b6 is set to '0' in case the erase is completed or in progress (see Table 12). The valid commands while erase is suspended are: Program/Erase Resume, Program, Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Block Protect, Block Unprotect and Block Lock. The user can protect the Block being erased issuing the Block Protect or Block Lock commands. During a block erase suspend, the device goes into standby mode by taking E to VIH, which reduces active current draw. Erase is aborted if RP turns to VIL. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by issuing the command D0h using an address within the suspended bank. The status register bit b6 and bit b7 are cleared when erase resumes and read M58MR032C, M58MR032D operations output the status register after the erase is resumed. Block erase cannot resume until program operations initiated during block erase suspend have completed. It is also possible to nest suspends as follows: suspend erase in the first partition, start programming in the second or in the same partition, suspend programming and then read from the second or the same partition. The suggested flowchart for erase suspend/resume features of the memory is shown from Figure 20. Program Suspend/Resume (PES/PER) Program suspend is accepted only during the Program instruction execution. When a Program Suspend command is written to the C.I., the P/E.C. freezes the Program operation. Program Resume (PER) continues the Program operation. Program Suspend (PES) consists of writing the command B0h and the address should be within the bank with the word in programming (see Table 11). The Status Register bit b2 is set to '1' (within 5s) when the program has been suspended. Bit b2 is set to '0' in case the program is completed or in progress (see Table 12). The valid commands while program is suspended are: Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature, CFI Query. During program suspend mode, the device goes in standby mode by taking E to VIH. This reduces active current consumption. Program is aborted if RP turns to VIL. If a Program Suspend instruction was previously executed, the Program operation may be resumed by issuing the command D0h using an address within the suspended bank (see Table 11). The status register bit b2 and bit b7 are cleared when program resumes and read operations output the status register after the erase is resumed (see Table 12). The suggested flowchart for program suspend/resume features of the memory is shown from Figure 18. Block Protect (BP) The BP instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Protect command 01h, written to an address within the block to be protected (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands (see Table 12). To read the status register write the RSR command. Block Unprotect (BU) The instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Unprotect command D0h, written to an address within the block to be protected (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands (see Table 12). To read the status register write the RSR command. Block Lock (BL) The instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Lock command 2Fh, written to an address within the block to be protected (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command (see Table 12). 17/52 M58MR032C, M58MR032D BLOCK PROTECTION The M58MR032C/M58MR032D provide a flexible protection of all the memory providing the protection, un-protection and locking of any blocks. All blocks are protected at power-up. Each block of the array has two levels of protection against programming or erasing operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: - when WP is at V IH, the Lock status is overridden and all blocks can be protected or unprotected; - when WP is at V IL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status; - the lock status is cleared for all blocks at power up. The protection and lock status can be monitored for each block using the Read Electronic Signature (RSIG) instruction. Protected blocks will output a '1' on DQ0 and locked blocks will output a '1' in DQ1 (see Table 13). PROTECTION REGISTER PROGRAM (PRP) and LOCK PROTECTION REGISTER PROGRAM (LPRP) The M58MR032C/M58MR032D features a 128-bit protection register and a security Block in order to increase the protection of a system design. The Protection Register is divided in two 64-bit segments. The first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be programmed by the user. When shipped the user programmable segment is read at '1'. It can be only programmed at '0'. The user programmable segment can be protected writing the bit 1 of the Protection Lock register (80h). The bit 1 protects also the bit 2 of the Protection Lock Register. The M58MR032C/M58MR032D feature a security Block. The security Block is located at 1FF0001FFFFF (M58MR032C) or at 000000-000FFF (M58MR032D) of the device. This block can be permanently protected by the user programming the bit 2 of the Protection Lock Register (see Figure 5). The protection Register and the Protection Lock Register can be read using the RSIG and RCFI instructions. A subsequent read in the address starting from 80h to 88h, the user will retrieve respectively the Protection Lock register, the unique device number segment and the OTP user programmable register segment (see Table 23). 18/52 WRITE READ CONFIGURATION REGISTER (CR). This instruction uses two Coded Cycles, the first write cycle is the write Read Configuration Register set-up 60h, the second write cycle is write Read Configuration Register confirm 03h both to Read Configuration Register address (see Table 11). This instruction writes the contents of address bits ADQ15-ADQ0 to bits CR15-CR0 of the Read Configuration Register (A20-A16 are don't care). At Power-up the Read Configuration Register is set to asynchronous Read mode, Power-down disabled and bus invert (power save function) disabled. A description of the effects of each configuration bit is given in Table 14. Read mode (CR15). The device supports an asynchronous page mode and a synchronous burst mode. In asynchronous page mode, the default at power-up, data is internally read and stored in a buffer of 4 words selected by ADQ0 and ADQ1 address inputs. In synchronous burst mode, the device latches the starting address and then outputs a sequence of data that depends on the Read Configuration Register settings (see Figures 10, 11 and 12). Synchronous burst mode is supported in both parameter and main blocks; it is also possible to perform burst mode read across the banks. Bus Invert configuration (CR14). This register bit is used to enable the BINV pin functionality. BINV functionality depends upon configuration bits CR14 and CR15 (see Table 14 for configuration bits definition) as shown in Table 15. As output pin BINV is active only when enabled (CR14 = 1) in Read Array burst mode (CR15 = 0). As input pin BINV is active only when enabled (CR14 = 1). BINV is ignored when ADQ0-ADQ15 lines are used as address inputs (addresses must not be inverted). X-Latency (CR13-CR11). These configuration bits define the number of clock cycles elapsing from L going low to valid data available in burst mode (see Figure 6). The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: - (n + 2) tK tACC + tQVK_CPU + tAVK_CPU - tK > tKQV + tQVK_CPU where "n" is the chosen X-Latency configuration code, tK is the clock period, tAVK_CPU is the address setup time guaranteed by the system CPU, and tQVK_CPU is the data setup time required by the system CPU. M58MR032C, M58MR032D Table 14. Read Configuration Register (AS and Read CFI instructions) (1) Configuration Register CR15 Function Read mode 0 = Synchronous Burst mode read 1 = Asynchronous Page mode read (default) Bus Invert configuration (power save) 0 = disabled (default) 1 = enabled X-Latency 010 = 2 clock latency 011 = 3 clock latency 100 = 4 clock latency 101 = 5 clock latency 111 = reserved Other configurations reserved Power-down configuration 0 = power-down disabled (default) 1 = power-down enabled Reserved Wait configuration 0 = WAIT is active during wait state 1 = WAIT is active one data cycle before wait state (default) Burst order configuration 0 = Interleaved 1 = Linear (default) Clock configuration 0 = Address latched and data output on the falling clock edge 1 = Address latched and data output on the rising clock edge (default) Reserved Burst Wrap 0 = burst wrap within burst length set by CR2-CR0 1 = Don't wrap accesses within burst length set by CR2-CR0 (default) Burst length 001 = 4 word burst length 010 = 8 word burst length 111 = Continuous burst mode (requires CR7 = 1) CR14 CR13-CR11 CR10 CR9 CR8 CR7 CR6 CR5-CR4 CR3 CR2-CR0 Note: 1. The RCR can be read via the RSIG command (90h). Bank A Address + 05h contains the RCR data. See Table 9. 2. All the bits in the RCR are set to default on device power-up or reset. Table 15. BINV Configuration Bits BINV CR15 0 0 1 1 CR14 IN 0 1 0 1 X Active X Active OUT 0 Active 0 0 19/52 M58MR032C, M58MR032D Power-down configuration (CR10). The RP pin may be configured to give very low power consumption when driven low (power-down state). In power-down the ICC supply current is reduced to a typical figure of ICC2; if this function is disabled (default at power-up) the RP pin causes only a reset of the device and the supply current is the stand-by value. The recovery time after a RP pulse is significantly longer when power-down is enabled (see Table 31). Wait configuration (CR8). In burst mode WAIT indicates whether the data on the output bus are valid or a wait state must be inserted. The configuration bit determines if WAIT will be asserted one clock cycle before the wait state or during the wait state (see Figure 7). WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. Burst order configuration (CR7) and Burst Wrap configuration (CR3). See Table 16 for burst order and length. Clock configuration (CR6). In burst mode determines if address is latched and data is output on the rising or falling edge of the clock. Burst length (CR2-CR0). In burst mode determines the number of words output by the memory. It is possible to have 4 words, 8 words or a continuous burst mode, in which all the words are read sequentially. In continuous burst mode the burst sequence can cross the end of each of the two banks (all banks in read array mode). In continuous burst mode or in 4, 8 words no-wrap it may happen that the memory will stop the data output flow for a few clock cycles; this event is signaled by WAIT going low until the output flow is resumed. The initial address determines if the output delay will occur as well as its duration. If the starting address is aligned to a four words boundary no wait states will be needed. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence is crossing the first 64 word boundary. WAIT will be asserted only once during a continuous burst access. See also Table 16. Figure 6. X-Latency Configuration Sequence K L A20-A16 VALID ADDRESS CONF. CODE 2 ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA VALID DATA VALID DATA CONFIGURATION CODE 3 ADQ15-ADQ0 VALID ADDRESS CONFIGURATION CODE 4 ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA AI90024 20/52 M58MR032C, M58MR032D Figure 7. Wait Configuration Sequence K L A20-A16 VALID ADDRESS ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' WAIT CR8 = '1' AI90025 21/52 Table 16. Burst Order and Length Configuration Starting Mode Address 4 Words Linear 0 1 2 3 ... 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 8 Words Continuous Burst Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... Wrap No-wrap 22/52 M58MR032C, M58MR032D 7 ... 60 61 62 63 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-65-66... Linear Interleaved Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 Interleaved 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 0 1 2 3 ... 7 ... 60 61 62 63 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13... 60-61-62-63 61-62-63-WAIT-64 62-63-WAIT-WAIT-64-65 63-WAIT-WAIT-WAIT-64-65-66 60-61-62-63-64-65-66-67 61-62-63-WAIT-64-65-66-67-68 62-63-WAIT-WAIT-64-65-66-67-68-69 63-WAIT-WAIT-WAIT-64-65-66-67-68-69-70 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-65-66... M58MR032C, M58MR032D POWER CONSUMPTION Power-down The memory provides Reset/Power-down control input RP. The Power-down function can be activated only if the relevant Read Configuration Register bit is set to '1'. In this case, when the RP signal is pulled at VSS the supply current drops to typically ICC2 (see Table 26), the memory is deselected and the outputs are in high impedance. If RP is pulled to VSS during a Program or Erase operation, this operation is aborted and the memory content is no longer valid (see Reset/Power-down input description). Power-up The memory Command Interface is reset on Power-up to Read Array. Either E or W must be tied to VIH during Power-up to allow maximum security and the possibility to write a command on the first rising edge of W. At Power-up the device is configured as: - Page mode: (CR15 = 1) - Power-down disabled: (CR10 = 0) - BINV disabled: (CR14 = 0). All blocks are protected and unlocked. VDD, V DDQ and VPP are independent power supplies and can be biased in any order. Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the V DD rails decoupled with a 0.1F capacitor close to the VDD, VDDQ and VSS pins. The PCB trace widths should be sufficient to carry the required VDD program and erase currents. 23/52 M58MR032C, M58MR032D COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardized data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Table 17. Query Structure Overview Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP Tables 17, 18, 19, 20, 21, 22 and 23 show the address used to retrieve each data. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode (see Table 11). Refer to the CFI Query instruction to understand how the M58MR032 enters the CFI Query mode. 80h Security Code Area Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs. Table 18. CFI Query Identification String Offset 00h 01h 02h 03h 04h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Sub-section Name 0020h 88DAh 88DBh reserved DRC (1) Description Manufacturer Code Device Code Reserved Die Revision Code Reserved Value ST Top Bottom reserved 0051h 0052h 0059h 0002h 0000h offset = P = 0039h 0000h 0000h 0000h value = A = 0000h 0000h "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 20) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table (0000h means none exists) p = 39h NA NA Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are `0'. 1. DRC means Die Revision Code. 24/52 M58MR032C, M58MR032D Table 19. CFI Query System Interface Information Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical timeout per single byte/word program = 2n s Typical timeout for tetra word program = 2n s Typical timeout per individual block erase = 2n ms Typical timeout for full chip erase = 2n ms Maximum timeout for word program = 2n times typical Maximum timeout for tetra word = 2n times typical Maximum timeout per individual block erase = 2n times typical Maximum timeout for chip erase = 2n times typical Value 1.7V 1Ch 0020h 2V 1Dh 0017h 1.7V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 00C0h 0004h 0004h 000Ah 0000h 0004h 0004h 0004h 0000h 12V 16s 16s 1s NA 512s 512s 16s NA 25/52 M58MR032C, M58MR032D Table 20. Device Geometry Definition Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0003h 0000h 0003h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within the device bit 7 to 0 = x = number of Erase Block Regions It specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. Region 1 Information (main block - Bank B) Number of identical-size erase block = 002Fh+1 Region 1 Information (main block - Bank B) Block size in Region 1 = 0100h * 256 byte Region 2 Information (main block - Bank A) Number of identical-size erase block = 000Eh+1 Region 2 Information (main block - Bank A) Block size in Region 2 = 0100h * 256 byte Region 3 Information (parameter block - Bank A) Number of identical-size erase block = 0007h+1 Region 3 Information (parameter block - Bank A) Block size in Region 3 = 0020h * 256 byte Region 1 Information (parameter block - Bank A) Number of identical-size erase block = 0007h+1 Region 1 Information (parameter block - Bank A) Block size in Region 1 = 0020h * 256 byte Region 2 Information (main block - Bank A) Number of identical-size erase block = 000Eh+1 Region 2 Information (main block - Bank A) Block size in Region 2 = 0001h * 256 byte Region 3 Information (parameter block - Bank B) Number of identical-size erase block = 002Fh+1 Region 3 Information (parameter block - Bank B) Block size in Region 3 = 0001h * 256 byte Value 4 MByte x16 Async. 8 Byte 3 2Dh 2Eh 2Fh 30h M58MR032C 31h 32h 33h 34h 35h 36h 37h 38h 2Dh 2Eh 2Fh 30h M58MR032D 31h 32h 33h 34h 35h 36h 37h 38h 002Fh 0000h 0000h 0001h 000Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0007h 0000h 0020h 0000h 000Eh 0000h 0000h 0001h 002Fh 0000h 0000h 0001h 48 64 KByte 15 64 KByte 8 8 KByte 8 8 KByte 15 64 KByte 48 64 KByte 26/52 M58MR032C, M58MR032D Table 21. Primary Algorithm-Specific Extended Query Table Offset (P)h = 39h Data 0050h 0052h 0049h (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0030h 00E6h 0003h (P+7)h (P+8)h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0" (P+9)h = 42h 0001h Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0' (P+A)h = 43h (P+B)h 0003h 0000h Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. Block protect Status Register Protect/Unprotect bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' bit 0 Yes Yes 1.8V (P+C)h = 45h 0018h VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV (P+D)h = 46h 00C0h VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV 12V (P+E)h = 47h (P+F)h (P+10)h (P+11)h (P+12)h 0000h Reserved 27/52 M58MR032C, M58MR032D Table 22. Burst Read Information Offset (P)+13h = 48h Data 0003h Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. 3 4 Description Value 8 Byte (P+14)h = 49h (P+15)h = 4Ah 0003h 0001h Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 bit 3-7 bit 0-2 Reserved 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. (P+16)h = 4Bh (P+17)h = 4Ch (P+18)h = 4Dh (P+19)h = 4Eh 0002h 0007h 0028h 0001h Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Max operating clock frequency (MHz) Supported handshaking signal (WAIT pin) bit 0 bit 1 during synchronous read during asynchronous read (1 = Yes, 0 = No) (1 = Yes, 0 = No) 8 Cont. 40 MHz Yes No Table 23. Security Code Area Offset 80h 81h 82h 83h 84h 85h 86h 87h 88h Data 0000-0000-0000-0XX0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 64 bits: User Programmable OTP 64 bits: unique device number Description Lock Protection Register 28/52 M58MR032C, M58MR032D Table 24. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 4ns 0 to VDDQ VDDQ/2 1N914 Figure 9. AC Testing Load Circuit VDDQ / 2 3.3k Figure 8. Testing Input/Output Waveforms DEVICE UNDER TEST CL = 30pF VDDQ/2 0V AI90026 OUT VDDQ CL includes JIG capacitance AI90027 Table 25. Capacitance (1) (TA = 25 C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. 29/52 M58MR032C, M58MR032D Table 26. DC Characteristics (TA = -40 to 85C; VDD = VDDQ = 1.7V to 2.0V) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current (Asynchronous Read Mode) ICC1 Supply Current (Synchronous Read Mode Continuous Burst) Supply Current (Power-down) Supply Current (Standby) Supply Current (Program or Erase) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH, f = 6MHz 10 Min Typ Max 1 5 20 Unit A A mA E = VIL, G = VIH, f = 40MHz 20 30 mA ICC2 ICC3 ICC4 (1) RP = VSS 0.2V E = VDD 0.2V Word Program, Block Erase in progress Program/Erase in progress in one Bank, Asynchronous Read in the other Bank Program/Erase in progress in one Bank, Synchronous Read in the other Bank VPP = 12V 0.6V VPP VCC VPP = 12V 0.6V -0.5 VDDQ -0.4 IOL = 100A IOH = -100A Program, Erase Double/Tetra Word Program VDDQ -0.1 VDDQ -0.4 11.4 2 15 10 10 50 20 A A mA 20 40 mA ICC5 (1) Supply Current (Dual Bank) 30 50 mA IPP1 VPP Supply Current (Program or Erase) VPP Supply Current (Standby or Read) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS VPP Supply Voltage VPP Supply Voltage Program or Erase Lockout 5 0.2 100 10 5 400 0.4 VDDQ + 0.4 0.1 mA A A V V V V IPP2 VIL VIH VOL VOH VPP1 VPPH VPPLK VDDQ + 0.4 12.6 1 V V V Note: 1. Sampled only, not 100% tested. 2. VPP may be connected to 12V power supply for a total of less than 100 hrs. 30/52 M58MR032C, M58MR032D Table 27. Asynchronous Read AC Characteristics (TA = -40 to 85C; VDD = VDDQ = 1.7V to 2.0V) M58MR032 Symbol Alt Parameter Test Condition Min tAVAV tAVLH tAVQV tAVQV1 tEHQX tEHQZ (1) tELLH tELQV (2) tELQX (1) tGHQX tGHQZ (1) tGLQV (2) tGLQX (1) tLHAX tLHGL tLLLH tLLQV tLLQV1 tAVDLAVDH tAVDLQV tRC tAVAVDH tACC tPAGE tOH tHZ tELAVDH tCE tLZ tOH tDF tOE tOLZ tAVDHAX Address Valid to Next Address Valid Address valid to Latch Enable High Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Latch Enable Low to Output Valid (Random) Latch Enable Low to Output Valid (Page) E = VIL, G = VIL G = VIH E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL, G = VIH G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL E = VIL, G = VIH E = VIL E = VIL, G = VIH E = VIL E = VIL 0 10 10 10 100 45 0 0 20 25 0 10 10 10 120 45 10 100 0 0 20 35 0 20 10 120 100 10 100 45 0 20 100 Max Min 120 10 120 45 120 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV . 31/52 32/52 tAVAV VALID ADDRESS tAVQV VALID ADDRESS tAVLH tLHAX VALID ADDRESS VALID DATA VALID ADDRESS tLLLH tLLQV tELLH tELQV tEHQZ tELQX tEHQX tGLQV tLHGL tGLQX tGHQX tGHQZ AI90028 M58MR032C, M58MR032D ADQ0-ADQ15 A16-A20 Figure 10. Asynchronous Read AC Waveforms L E G Note: Write Enable (W) = High. ADQ0-ADQ15 VALID DATA VALID ADDRESS VALID DATA VALID ADDRESS VALID DATA VALID ADDRESS VALID ADDRESS VALID DATA Figure 11. Page Read AC Waveforms tAVLH VALID ADDRESS tLLQV1 tLHAX tAVQV1 A16-A20 tLLQV L tELQV E tGLQV G tLHGL tGHQZ AI90029 M58MR032C, M58MR032D 33/52 M58MR032C, M58MR032D Table 28. Synchronous Burst Read AC Characteristics (TA = -40 to 85C; VDD = VDDQ = 1.7V to 2.0V) M58MR032 Symbol Alt Parameter Test Condition Min tAVK tELK tK tKAX tKHKL tKLKH tKQV tAVCLKH tCELCLKH tCLK tCLKHAX tCLKHCLKL tCLKLCLKH tCLKHQV Address Valid to Clock Chip Enable Low to Clock Clock Period Clock to Address Transition Clock High Clock Low Clock to Data Valid Clock to BINV Valid Clock to WAIT Valid Clock to Output Transition Clock to BINV Transition Clock to WAIT Transition Latch Enable High to Address Transition Latch Enable Low to Clock E = VIL, G = VIL E = VIL, G = VIH 7 7 25 13 5 5 20 100 Max Min 7 7 25 13 5 5 20 120 Max ns ns ns ns ns ns ns Unit tKQX tCLKHQX E = VIL 4 4 ns tLHAX tLLK tADVHAX tAVDLCLKH 13 7 13 7 ns ns 34/52 ADQ0-ADQ15 VALID VALID VALID VALID DATA VALID ADDRESS A16-A20 VALID ADDRESS tAVLH tLLLH L tKQV tKQX tEHQX tEHQZ note 1 tKAX tK Figure 12. Synchronous Burst Read tLLK tAVK K tELK E tGLQX tGHQX tGHQZ G tKQX VALID VALID tKQV note 2 note 3 tKQX AI90030 BINV VALID tKQV WAIT M58MR032C, M58MR032D Note: 1. The number of clock cycles to be inserted depends upon the x-latency set in the read configuration register. 2. WAIT signal can be configured to be active during wait state or one cycle below wait state. 3. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information). 35/52 M58MR032C, M58MR032D Table 29. Write AC Characteristics, Write Enable Controlled (TA = -40 to 85 C; VDD = V DDQ = 1.7V to 2.0V) M58MR032 Symbol Alt Parameter Min tAVAV tAVLH tDVWH tELLH tELWL tGHLL tGHWL tLHAX tLHWH tLLLH tVDHEL tVPPHWH tWHDX tWHEH tWHGL tWHLL tWHVPPL tWHWL tWHWPV tWLWH tWPVWH tWP tWPH tDH tCH tOEH tVCS tCS tDS tWC Address Valid to Next Address Valid Address Valid to Latch Enable High Input Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Output Enable High to Latch Enable Low Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable High to Write Enable High Latch Enable Pulse Width VDD High to Chip Enable Low VPP High to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Latch Enable Low Write Enable High to VPP Low Write Enable High to Write Enable Low Write Enable High to Write Protect Valid Write Enable Low to Write Enable High Write Protect Valid to Write Enable High 100 10 40 10 0 20 20 10 10 10 50 200 0 0 0 0 200 30 200 50 200 100 Max Min 120 10 40 10 0 20 20 10 10 10 50 200 0 0 0 0 200 30 200 50 200 120 Max ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns Unit 36/52 tAVAV ADDRESS VALID DATA VALID ADQ0-ADQ15 A16-A20 tAVLH VALID tLLLH tLHWH tWHLL tLHAX tDVWH tWHDX ADDRESS VALID BINV L tWLWH W tELLH tELWL tWHGL Figure 13. Write AC Waveforms, W Controlled E G tGHLL tGHWL tWPVWH VALID tVPPHWH VPPH VPP1 tWHVPPL tWHWPV WP tVDHEL VPP VDD AI90031 M58MR032C, M58MR032D 37/52 M58MR032C, M58MR032D Table 30. Write AC Characteristics, Chip Enable Controlled (TA = -40 to 85 C; VDD = V DDQ = 1.7V to 2.0V) M58MR032 Symbol Alt Parameter Min tAVAV tAVLH tDVEH tEHDX tEHEL tEHWH tELEH tELLH tGHLL tLHAX tLHEH tLLLH tVDHEL tVPPHEH tEHVPPL tEHWPV tWLEL tWPVEH tWS tVCS tDS tDH tCPH tWH tCP tWC Address Valid to Next Address Valid Address Valid to Latch Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Chip Enable High Latch Enable Pulse Width VDD High to Chip Enable Low VPP High to Chip Enable High Chip Enable High to VPP Low Chip Enable High to Write Protect Valid Chip Enable Low to Chip Enable Low Write Protect Valid to Chip Enable High 100 10 40 0 30 0 60 10 20 10 10 10 50 200 200 200 0 200 100 Max Min 120 10 40 0 30 0 60 10 20 10 10 10 50 200 200 200 0 200 120 Max ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns Unit 38/52 ADQ0-ADQ15 ADDRESS VALID DATA VALID A16-A20 tAVLH VALID tLLLH tLHEH tLHAX tDVEH tEHDX ADDRESS VALID BINV L tEHWH tWLEL W tELLH tELEH tEHEL Figure 14. Write AC Waveforms, E Controlled E G tGHLL tWPVEH VALID tVPPHEH VPPH VPP1 tEHVPPL tEHWPV WP tVDHEL VPP VDD AI90032 M58MR032C, M58MR032D 39/52 M58MR032C, M58MR032D Figure 15. Reset and Power-up AC Waveforms L, W, E, G tPHWL tPHEL tPHGL RP tVDHPH VDD, VDDQ Power-up AI90033 tPHWL tPHEL tPHGL tPLPH Table 31. Reset and Power-up AC Characteristics Symbol tPLPH (1,2) tPHEL tPHLL tPHWL tVDHPH (3) Parameter RP Pulse Width During Program and Erase Reset High to Device Enabled Other Conditions Supply Valid to Reset High 30 50 ns s Test Condition Min 100 50 Unit ns s Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset. Table 32. Program, Erase Times and Program, Erase Endurance Cycles (TA = -40 to 85C; VDD = VDDQ = 1.7V to 2.0V, VPP = VDD unless otherwise specified) Parameter Parameter Block (4 K-Word) Erase (Preprogrammed) Main Block (32 K-Word) Erase (Preprogrammed) Bank Erase (Preprogrammed, Bank A) Bank Erase (Preprogrammed, Bank B) Chip Program (2) Chip Program (DPG, VPP = 12V) (2) Word Program (3) Double Word Program Tetra Word Program Program/Erase Cycles (per Block) 100,000 200 200 200 Min Max (1) 2.5 10 Typ 0.5 1 4 15 40 20 10 10 10 10 10 10 Typical after 100k W/E Cycles 1 3 Unit sec sec sec sec sec sec s s s cycles Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or erase should perform significantly better. 2. Excludes the time needed to execute the sequence for program instruction. 3. Same timing value if V PP = 12V. 40/52 M58MR032C, M58MR032D Figure 16. Program Flowchart and Pseudo Code (1) Start Write 40h or 10h Command Write Address & Data Program instruction: - write 40h or 10h command - write Address & Data (memory enters read status state after the Program instruction) NO Read Status Register Suspend NO YES Suspend Loop do: - read status register (E or G must be toggled) if PES instruction given execute suspend program loop b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End while b7 = 1 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: - error handler NO Program Error (1, 2) If b4 = 1, Program error: - error handler NO Program to Protected Block Error (1, 2) If b1 = 1, Program to protected block error: - error handler AI90034 Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after a program sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 41/52 M58MR032C, M58MR032D Figure 17. Double Word Program and Tetra Word Program Flowchart and Pseudo code (1) Start Write 55h Command Write Address 1 & Data 1 Write Address 2 & Data 2 DPG instruction: - write 30h command - write Address 1 & Data 1 (3) - write Address 2 & Data 2 (3) (memory enters read status state after the Program instruction) Write Address 3 & Data 3 Write Address 4 & Data 4 TPG instruction: - write 55h command - write Address 1 & Data 1 (4) - write Address 2 & Data 2 (4) - write Address 3 & Data 3 (4) - write Address 4 & Data 4 (4) (memory enters read status state after the Program instruction) do: - read status register (E or G must be toggled) if PES instruction given execute suspend program loop YES Suspend Loop while b7 = 1 NO Read Status Register Suspend NO b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: - error handler NO Program Error (1, 2) If b4 = 1, Program error: - error handler NO Program to Protected Block Error (1, 2) If b1 = 1, Program to protected block error: - error handler AI90035 Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a program sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 3. Address 1 and address 2 must be consecutive addresses differing only for address bit A0. 4. Address, address 2, address 3 and address 4 must be consecutive addresses differing only for address bit A1-A0. 42/52 M58MR032C, M58MR032D Figure 18. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command Write 70h Command PES instruction: - write B0h command do: - read status register (E or G must be toggled) Read Status Register b7 = 1 YES b2 = 1 YES Write a read Command NO while b7 = 1 NO Program Complete If b2 = 0 Program completed Read data from another address Write D0h Command Write FFh Command Program Continues Read Data PER instruction: - write D0h command to resume the program - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI90036 43/52 M58MR032C, M58MR032D Figure 19. Block Erase Flowchart and Pseudo Code Start Write 20h Command Write Block Address & D0h Command EE instruction: - write 20h command - write Block Address (A12-A20) & command D0h (memory enters read status state after the EE instruction) do: - read status register (E or G must be toggled) if PES instruction given execute suspend erase loop YES Read Status Register NO Suspend b7 = 1 NO Suspend Loop while b7 = 1 YES b3 = 0 YES b4, b5 = 0 YES b5 = 0 YES b1 = 0 YES End NO Erase to Protected Block Error (1) NO Erase Error (1) NO Command Sequence Error (1) NO VPP Invalid Error (1) If b3 = 1, VPP invalid error: - error handler If b4, b5 = 1, Command sequence error: - error handler If b5 = 1, Erase error: - error handler If b1 = 1, Erase to protected block error: - error handler AI90037 44/52 M58MR032C, M58MR032D Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command Write 70h Command PES instruction: - write B0h command do: - read status register (E or G must be toggled) Read Status Register b7 = 1 YES b6 = 1 YES NO while b7 = 1 NO Erase Complete If b6 = 0, Erase completed Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Command Write FFh Command Erase Continues Read Data PER instruction: - write D0h command to resume erasure - if the erase operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI90038 45/52 M58MR032C, M58MR032D Table 33. Command Interface States - Lock table Current State of the Current Partition Current State of the Other Partition Command Input to the Current Partition (and Next State of the Current Partition) Erase Read Confirm P/ Read Memory E Resume Status Array BU Register (FFH) Confirm (70h) (D0h) Block ProtectUnprotectLock setup write RCR setup (60h) Block ProtectUnprotectLockSetup Write RCR Setup Block ProtectUnprotectLockError Write RCR Error Mode State Others Clear Read Status Read CFI elect. Register (98h) sign. (90h) (50h) Block Protect Confirm (01h) Block Write RCR Lock Confirm Confirm (03h) (2Fh) Any State Read Array CFI Electronic Signature Status SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Read CFI Read Array Read Array Read Array Setup Protect Any State Unprotect Lock RCR Block Block Block Block Block Block ProtectProtectProtectProtectBlock ProtectProtectUnprotect- Unprotect- Protect- Unprotect- Unprotect- Unprotect- UnprotectLockError LockError Unprotect- LockError LockError LockError LockError Write RCR Write RCR LockBlock Write RCR Write RCR Write RCR Write RCR Error Error Error Error Error Error Block Block ProtectProtectSet RCR Unprotect- UnprotectLockBlock LockBlock Error ProtectUnprotectLockBlock Set RCR SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Block ProtectUnprotectRead CFI Read Array Read Array Read Array LockSetup Write RCR Setup Block ProtectUnprotectRead Array Read Array Read Array Read CFI LockSetup Write RCR Setup Block ProtectUnprotectRead CFI Read Array Read Array Read Array LockSetup Write RCR Setup PS Read CFI Erase Error PS Read Array PS Read Array PS Read Array PS Read Array Any State Protection Register Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Any State ProgramMultiple Program Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Setup Idle Erase Suspend Idle Program Suspend Read Array, CFI, Elect. Sign., Status Setup Error SEE MODIFY TABLE Erase Error PS Read Array Erase Error Program (Busy) Erase (Busy) PS Read Status Register Erase Error PS Read Array Erase Error PS Read Elect. Sign. Erase Error Read Elect. Sign. Any State Block-Bank Erase Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Erase (Busy) ES Read Array Erase (Busy) ES Read Array Erase Erase Erase Erase Error Error Error Error Block ProtectUnprotectRead Array Read Array Read Array Read CFI LockSetup Write RCR Setup Block ProtectES Read Unprotect- ES Read CFI LockSetup Array Write RCR Setup Setup Busy Idle Program Suspend Read Array, CFI, Erase Elect. Suspend Sign., Status SEE MADIFY TABLE ES Read Array ES Read Status Register ES Read Array ES Read Elect. Sign. ES Read Array ES Read Array 46/52 M58MR032C, M58MR032D Table 34. Command Interface States - Modify table Current State of the Other Partition Setup Busy Idle Erase Suspend Program Suspend Setup Busy Read Current State of the Current Partition Mode State Others Command Input to the Current Partition (and Next State of the Current Partition) Program Setup (10h/40h) Read Array Array, CFI, Electronic Signature, Status Register SEE LOCK TABLE Block Erase Setup (20h) Read Array Block Erase Setup Read Array Read Array Block Erase Setup Read Array Read Array Read Array Program-Erase Suspend (B0h) OTP Setup (C0h) Read Array OTP Setup Read Array Read Array OTP Setup Read Array Multiple Program Setup (30h/55h) Read Array Multiple Program Setup Read Array Read Array Multiple Program Setup Read Array Bank Erase Setup (80h) Read Array Bank Erase Setup Read Array Read Array Bank Erase Setup Read Array Program setup Read Array Read Array Error, ProtectProtect Idle UnprotectSEE LOCK Unprotect-Lock/ LockBlock, Set TABLE RCR Erase Suspend RCR Program Suspend Idle Setup Protection Register (Busy) Setup Busy Busy Protection Idle Register SEE LOCK Done TABLE Erase Suspend Program Suspend Any State Setup Program (Busy) Idle Busy Setup Busy Idle Erase Suspend Program Suspend Setup Idle Erase Suspend ProgramMultiple Program Program setup Read Array Protection Protection Protection Protection Protection Protection Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Read Array Program Setup Read Array Read Array Block Erase Setup Read Array Read Array OTP Setup Read Array Read Array Read Array Multiple Program Setup Read Array Read Array Bank Erase Setup Read Array Program (Busy) Program (Busy) Program (Busy) PS Read Status Program (Busy) Program (Busy) Program (Busy) Register Read Array Read Array Block Erase Setup Read Array Read Array Read Array OTP Setup Read Array Read Array Multiple Program Setup Read Array Read Array Bank Erase Setup Read Array Done SEE LOCK TABLE Program Setup Read Array Program Suspend Read Array, CFI, Elect. Sign., Status Register Setup Busy SEE LOCK TABLE SEE LOCK TABLE Erase (Busy) PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array Idle Setup Busy Idle Program Suspend Block-Bank Erase Erase Error Erase (Busy) ES Read Array Erase Error Erase (Busy) Erase Error ES Read Status Register Erase Error Erase (Busy) Erase Error Erase (Busy) ES Read Array Erase Error Erase (Busy) Erase Suspend Read Array, CFI, Elect. Sign., Status Register SEE LOCK TABLE Program Setup ES Read Array ES Read Array ES Read Array ES Read Array Multiple ES Read Array Program Setup ES Read Array 47/52 M58MR032C, M58MR032D Table 35. Ordering Information Scheme Example: Device Type M58 Architecture M = Multiplexed Address/Data, Dual Bank, Burst Mode Operating Voltage R = 1.8V Device Function 032C = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot 032D = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot Speed 100 = 100 ns 120 = 120 ns Package ZC = TFBGA48: 0.5 mm pitch Temperature Range 6 = -40 to 85C Option T = Tape & Reel packing M58MR032C 100 ZC 6 T Devices are shipped from the factory with the memory content bits erased to '1'. Table 36. Daisy Chain Ordering Scheme Example: Device Type M58MR032 Daisy Chain -ZC = TFBGA48: 0.5 mm pitch Option T = Tape & Reel Packing M58MR032 -ZC T For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 48/52 M58MR032C, M58MR032D Table 37. Document Revision History Date November 2000 12/20/00 Version -01 -02 First Issue Protection/Security clarification FBGA Connections change (Figure 2) Memory Map diagram clarification (Figure 3) Single Synchronous Read clarification (Figure 4) Identifier Codes clarification (Table 9) X-Latency configuration clarification CFI Query Identification String change (Table 18) Synchronous Burst Read Waveforms change (Figure 12) Reset AC Characteristics clarification (Table 31) Program Time clarification (Table 32) TFBGA Package Mechanical and Outline drawing change (Table 27, Figure 21) Reset AC Characteristics clarification (Table 31) Reset AC Waveforms diagram change (Figure 15) Document type: from Target Specification to Product Preview Write AC Waveforms W Contr. change (Figure 13) Reset and Power-up AC Characteristics and Waveform change (Table 31, Figure 15) TFBGA Package Mechanical Data change (Table 38) TFBGA Package Mechanical Data change Reset and Power-up AC Characteristics clarification Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 05 becomes 5.0). Supply voltage ranges VDD and VDDQ modified, Burst mode Read frequency modified. Maximum operating frequency modified in Table 22, Burst Read Information. Parameters tK, tKQV, tKAX and tLHAX modified in Table 28, Synchronous Burst Read AC Characteristics. Document status changed from Product Preview to Preliminary Data. Revision Details 1/08/01 3/02/01 -03 -04 3/19/01 01-Aug-2002 -05 5.1 49/52 M58MR032C, M58MR032D Table 38. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data Symbol A A1 A2 b D D1 D2 D3 ddd E E1 E2 E3 e FD FD1 FD2 FE FE1 FE2 SD SE Typ millimeters Min 0.950 0.200 0.250 10.480 - - - 6.240 - - - - - - - - - - - - Max 1.200 0.300 0.350 10.580 - - - 0.080 6.340 - - - - - - - - - - - - Typ inches Min 0.0374 0.0079 0.0098 0.4126 - - - 0.2457 - - - - - - - - - - - - Max 0.0472 0.0118 0.0138 0.4165 - - - 0.0031 0.2496 - - - - - - - - - - - - 0.790 0.300 10.530 4.500 6.500 8.500 6.290 1.500 3.500 5.500 0.500 3.015 2.015 1.015 2.395 1.395 0.395 0.250 0.250 0.0311 0.0118 0.4146 0.1772 0.2559 0.3346 0.2476 0.0591 0.1378 0.2165 0.0197 0.1187 0.0793 0.0400 0.0943 0.0549 0.0156 0.0098 0.0098 Figure 21. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline D D3 D2 D1 FE FE1 FE2 SD E1 e SE E2 E3 E BALL "A1" FD2 FD1 FD b DUMMY BALLS ddd A A1 A2 BGA-Z17 Drawing is not to scale. 50/52 M58MR032C, M58MR032D Figure 22. TFBGA48 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H AI90039 Figure 23. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B START POINT C D E F G END POINT H AI90040 51/52 M58MR032C, M58MR032D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 52/52 |
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